1. Field of the Invention
The present invention is concerned with new fill compositions for use in the manufacture of microelectronic devices, particularly dual damascene structures.
2. Description of the Prior Art
As integrated circuit devices grow smaller, there is an increasing need for multi-level interconnects of smaller size and improved feature integrity. The damascene integration scheme is one way to allow for increasing chip densities on a substrate as design rules continue to shrink integrated circuit devices. The damascene process eliminates the need to etch the metal layer that provides the interconnections, permits more densely spaced interconnects, and eliminates the need for dielectric gap-fill materials.
There are two general classes of damascene processes: single damascene and dual damascene. The single damascene process fabricates interconnections by forming a conducting plug through a dielectric layer to connect to the underlying conducting layer. Another dielectric layer is then formed, with the actual interconnect wiring metallization being patterned in the second layer. The dual damascene process constructs multi-level interconnects of smaller size than the single damascene process. Horizontal trenches and vertical holes (i.e., the contact and via holes) are patterned into a single dielectric layer and then filled in one step with a conducting material such as a metal. Dual damascene processes involve fewer steps, resulting in smaller, more complex integrated circuit devices, thus lowering manufacturing complexity and cost.
Despite the advantages of dual damascene processes, patterning and etch processes are made more difficult because of feature topography and more complex stack layers. Several techniques have been developed to address such problems, including self-aligned dual damascene, trench-first dual damascene, and via-first dual damascene processes. The application of self-aligned dual damascene is limited, because it requires a thick, intermediate layer to act as an anti-reflective layer, nearly perfect trench and via alignment, and very high etch selectivity between the dielectric and etch-stop layers. Trench-first dual damascene processes involve first masking and etching the trench, and then aligning the via pattern with the newly etched trenches. Successful trench-first dual damascene processes require achieving very uniform trenches and maintaining critical dimension control of vias, which in turn requires high etch selectivity between the dielectric and etch-stop layers. The use of etch-stop layers may also increase the dielectric constant of the dielectric material, possibly leading to device failure.
Via-first dual damascene is a somewhat simpler technique, because the vias are formed on top of the full stack of layers. The vias are etched, followed by lithography processes to form the trench patterns. Formation of the trench patterns exposes the bottom and sidewalls of the vias to over-etch. Via-first dual damascene requires a fill composition capable of protecting the bottom and sidewalls of the via during the trench etch step, and of planarizing the surface to allow easier trench patterning. Two techniques are commonly used in via-first dual damascene processes: partial fill and full fill. In partial fill processes, the fill material protects only the bottoms of the via holes, requiring consistent coverage and depth control. In full-fill processes, the vias are completely filled and the layer is pianarized. The etching process is performed on the top layer.
In either process, once the pattern is created, the remaining fill material in the vias and trenches must be removed so that metal can be deposited in the vias and trenches and the connections made. Traditionally, this removal has been accomplished by an oxygen plasma ash process, which essentially burns away the material. This technique was suitable for older technology; however, as the industry moves toward lower k dielectrics, potential problems arise. For example, these low-k dielectrics and ultralow-k dielectrics are usually organic, instead of inorganic, and some are porous. Thus, these new dielectric materials are very susceptible to etch damage, especially from the oxygen ash process. One concern is that the conventional clean-out techniques can cause an increase in the dielectric constant of the layer, which is detrimental to device performance and negates the purpose of a low-k dielectric to begin with.
Thus, there is a need for new fill materials and processes whereby the remaining material in the via hole can be easily removed without the harsh ash process.